1. Field of the Invention
The present invention relates to a timing calibration method of a semiconductor testing apparatus and also relates to a semiconductor device testing apparatus having the timing calibration function which can test a semiconductor device including memories, logic circuits and the like.
2. Description of the Related Art
FIG. 7 shows a briefly illustrated generally known semiconductor device testing apparatus. The semiconductor device testing apparatus comprises a computer system 10 operating as a controller of the semiconductor device testing apparatus, a pattern generator 11, a pin data selector 12, a waveform formatter group 13, a timing calibrator group 14, a driver group 15, an output pin group 16, a device power supply source 17, a logical comparator 18, a failure analysis memory 19. A semiconductor device under test which is hereinafter referred to as DUT is turned into its operating state upon receipt of a power supply voltage from the device power supply source 17, and test pattern signals (TPS) delivered to the output pin group 16 are supplied to input pins or input/output pins for both signal input and output use of DUT.
The pattern generator 11 outputs test pattern data (TPD) for a plurality of channels. These test pattern data are distributed to the respective input pins as respective pin data for DUT.
The waveform formatter group 13 includes waveform formatters (13-1, 13-2, 13-3, - - - ) the number of which is sufficient to cover the number of channels corresponding to the input pins of DUT. When a plurality of DUTs are simultaneously tested, waveform formatters, the number of which is equal to the number of devices multiplied by the number of channels, are to be provided. Each test pattern data distributed as each pin data is shaped to a test pattern signal (TPS) having a waveform that meets standard requirements (for example, amplitude value) of the semiconductor device to be tested DUT, and this test pattern signal is delivered via the timing calibrator group 14 (14-1, 14-2, 14-3, - - - ) and the driver group 15 (15-1, 15-2, 15-3, - - - ) to the output pin group 16 (P1, P2, P3, - - - ).
Now, hereinafter each signal transmission channel through which each test patter signal is delivered from the waveform formatter, via the timing calibrator and the driver to each output pin, is referred to as a test pattern signal transmission path of each channel of the semiconductor device testing apparatus.
In the case where DUT is a memory, the test pattern signal at the output pin is applied to input terminal of DUT and is written or stored in the memory of DUT. The test pattern signal thus written in DUT is then read out therefrom at its output terminal as output data (OPD) which is in turn compared with an expected value data (EPD) by the logical comparator 18.
When a discordance is detected by the logical comparator 18, an address of the memory at which the discordance is detected, the test pattern by which the discordance is caused, and the like are stored in the failure analysis memory 19, and are utilized in a failure analysis, a failure relief processing, or the like.
Among test items of a semiconductor device to be tested DUT, there is a test for inspecting response characteristics of DUT, which includes, for example, an inspection of a marginal phase range in which DUT can maintain its operable condition by shifting the phase of the test pattern signal to be applied to an input terminal of DUT toward advancing direction or delaying direction from a reference phase position by varying timing of a timing signal generated by a timing generator (although not shown in the drawings), or another inspection of a marginal timing delay in an output timing of the read out data from a timing at which a read command signal is applied to DUT.
When the test of this type is performed, it is necessary that respective signal propagation time values for respective test pattern signal transmission paths each being constituted by a waveform formatter, a tuning calibrator, and a driver should be aligned to have a same constant value. A work for aligning the respective signal propagation time values of respective test pattern signal transmission paths to a constant value is referred to as a timing calibration. In order to perform this timing calibration mode, there is provided a specific arrangement including the timing calibrator group 14, a pin selection device 21, and a timing measurement device 22.
FIG. 8 shows a previously developed testing apparatus within a facility of the Assignee of the present invention which shows a connection state of the testing apparatus in its timing calibration mode, wherein the pin selection device 21 is connected to a group 16 of output pins P1, P2, P3, - - - , and any one of the output pins in their output pin group 16 is selectively connected by the pin selection device 21 to the timing measurement device 22.
As the timing measurement device 22 for use in the timing calibration mode, for example, an oscilloscope or any timing measurement means usually equipped in a semiconductor device testing apparatus of this type can be used.
In the timing calibration mode of the testing apparatus as shown in FIG. 8, the pattern generator 11 generates a timing calibration pulse data, TPD which is designed to form a timing calibration pulse PT having a predetermined constant duration period at the respective waveform formatters.
The pin data selector 12 distributes the timing calibration pulse data TPD, from the pattern generator to the respective waveform formatters (13-1, 13-2, - - - ), so that the timing calibration pulse (PT) is generated by each of the respective waveform formatters and is transmitted through respective test pattern signal transmission paths to the respective output pins (P1, P2, - - - ), respectively.
Now assuming one of the output pins, for example, P1 in FIG. 8 as a reference output pin.
The timing calibration pulse signals (PT) having the constant duration period as shown in FIG. 9 is transmitted to the predetermined reference output pin, P1 in FIG. 8 via a reference test pattern signal transmission path which is composed of a series connection circuit of a waveform formatter 13-1, a timing calibrator 14-1, and a driver 15-1, and is then selectively transmitted to the timing measurement device 22 by a pin selection device 21.
FIG. 10 shows an example of internal circuit structure of the pin selection device 21. In this example, there is shown a case of circuit structure in which the reference output pin P1 of the output pin group 16 can be connected to the output terminal TOU by switching operations of relay switches RS1-1 through RS4-1. In the example of FIG. 10, there is shown a state that the relay switches RS1-1, RS 2-1, RS3-1 and RS4-1 are connected to a contact side (a), which is referred to as a pin selection path for the reference output pin P1 in the pin selection device 21.
In the case of using an oscilloscope as the timing measurement device 22, a rising timing of the thus transmitted timing calibration pulse PT is measured using a scale on the lateral X axis that is a time axis on the display screen (OSD) of the oscilloscope, and that scale position is determined as a reference phase position (RPP). (See FIG. 9) The timing calibration pulses (PT) are transmitted to the respective remaining output pins P2, P3, - - - via the corresponding test pattern signal transmission paths and also selectively connected one after another to the oscilloscope. The corresponding delay time values of the timing calibrators 14-2, 14-3, - - - in the respective test pattern signal transmission paths for the remaining output pins P2, P3, - - - other than the reference output pin P1 are adjusted to perform the timing calibration such that a rising timing of the outputted pulse sequence at each one of the remaining output pins is accorded with the reference phase position (RPP).
The characteristic of this pin selection device 21 is that a consideration is made such that whenever any one of the output pins P1-P16 is selected, the line length of the pin selection path from each of the output pins P1-P16 to the output terminal TOU should become equal to each other, and hence even if any one of the output pins P1-P16 is selected, the delay time value in the pin selection device is equal to a constant value.
Moreover, signal conductors in the pin selection device 21 are formed by printed wiring, and is constructed in micro-strip-line structure so that specific characteristic impedance can be obtained in order to especially prevent a waveform of a high-speed pulse signal from being deteriorated.
However, it is difficult to make all of the signal propagation delay time values of those pin selection paths equal to a constant value, and in reality, a slight difference in delay time value might inevitably occurs between the pin selection paths.
If it is assumed that a difference in the delay time value might exist between the pin selection paths in the pin selection device 21, this time difference is erroniously added to or included into the timing calibration value which is determined by and set forth in the timing calibrators 14 when the timing calibration is completed. Hence, in this case, there is a drawback that the internal difference in the delay time values of the pin selection paths of the pin selection device 21 is summed as a timing error into the timing calibration value.
FIG. 11 shows the above stated drawback. In FIG. 11, a reference sign TS represents a constant delay time value to which the respective delay time values of the respective channels are to be adjusted equally. As assumed before, the respective pin selection paths for the respective output pins have their delay time values (TA-1, TA-2, TA-3, - - - ) which are slightly different from each other.
In the calibration mode, however, the delay time values of the respective remaining channel are adjusted to be equal to the constant time TS by adjusting the respective calibrators 14-1, 14-2, 14-3, - - - .
As it is seen in FIG. 11, within the constant time length TS, the breakdowns of the delay time values of respective channels are sums of corresponding delay time values (TX1, TX2, TX3, - - - ) caused by the respective signal transmission paths of the semiconductor device testing apparatus and corresponding delay time values (TA1, TA2, TA3, - - - ) (hatched portions) caused by the respective pin selection paths in the pin selection device 21. If the delay time values TA2, TA3 . . . caused by the respective pin selection paths for the remaining output pins P2, P3, - - - in the pin selection device 21 are either longer or shorter than that (TA-1) of the reference pin selection path, time differences caused by delay time value dispersion of the respective pin selection paths in the pin selection device 21 are reflected in the delay time values (TX2, TX3, - - - ) caused by the respective test pattern signal transmission paths for the remaining output pins.
Therefore, in the state that the pin selection device 21 is detached after the timing calibration, the delay time values (TX1, TX2, TX3, - - - ) caused by the respective test pattern signal transmission paths include the delay time value differences of the pin selection device 21 respectively, and hence it can hardly be said that the timing calibration is correctly performed.
Further, as the pin selection device 21, in addition to the configuration shown in FIG. 10, there may be another pin selection device having a structure wherein a probe is utilized which is movable in X-Y-Z orthogonal directions by an X-Y-Z orthogonal driving mechanism, and an input terminal of the timing measurement device 22 is connected to the output pin group 16 by the probe. Even in the pin selection device having this structure, when the probe is moved in X-Y-Z directions, the curvature of the cable (coaxial cable) connecting the probe to the timing measurement device changes. There occurs a phenomenon that the delay time value of the cable is changed due to the change of the curvature, and hence there is a problem similar to that of the case described above.
It is an object of the present invention to propose a timing calibration method of a semiconductor device testing apparatus by which the problem described above is solved and the signal propagation delay time value differences in the pin selection device 21 are not reflected as errors in the timing calibration of the semiconductor device testing apparatus, and to propose the semiconductor device testing apparatus that has an arrangement on board for materializing this calibration method.
In order to achieve the above object, in the first aspect of the present invention, there is proposed a timing calibration method for a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths through which test pattern signals are transmitted to output pins and testing a semiconductor device under test using the thus transmitted test pattern signals, wherein the timing calibration method comprises the steps of: selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths which are provided to correspond to the output pins, respectively; measuring by means of the timing measurement device signal propagation delay time values through the respective pin selection paths and storing the measured values in a memory; measuring by means of the timing measurement device total signal propagation delay time values through respective series connections each of which is constituted of one of the test pattern signal transmission paths and one of the pin selection paths corresponding to the respective output pins; subtracting the memorized values of the respective pin selection paths from the corresponding total signal propagation delay time values to thereby obtain difference delay time values; and adjusting delay time values of timing calibrators in the respective test pattern signal transmission paths such that those respective difference delay time values corresponding to all the output pins accord with a predetermined value whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.
In the second aspect of the present invention, there is proposed a timing calibration method in a semiconductor device testing apparatus comprising a plurality of test pattern signal transmission paths through which test pattern signals are transmitted to output pins and testing a semiconductor device under test using the thus transmitted test pattern signals, wherein the timing calibration method comprises the steps of: selectively connecting the respective output pins one after another to a timing measurement device through respective pin selection paths which are provided to correspond to the output pins, respectively; measuring by means of the timing measurement device signal propagation delay time values through the respective pin selection paths and storing the measured values in a memory; determining one of the output pins as a reference output pin and calculating deviation values between the delay time value as a reference value through the pin selection path for the reference output pin and respective delay time values through remaining pin selection paths for remaining output pins other than the reference output pin; measuring by means of the timing measurement device total signal propagation delay time vales through respective series connections each of which is constituted of one of the test pattern signal transmission paths and one of the pin selection paths; calculating deviation values between the total signal propagation delay time value for the reference output pin and the respective total signal propagation delay time values; and adjusting signal propagation delay time values of timing calibrators in the respective test pattern signal transmission paths for the remaining output pins such that those deviation values of the total delay time values for the respective remaining output pins accord with the corresponding deviation values, respectively whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.
In the third aspect of the present invention, there is proposed a semiconductor device testing apparatus having a timing calibration mode comprising: a pattern generator; a pin data selector distributing pin data including test pattern data, address signals and control signals, and outputted from the pattern generator to respective pin channels corresponding to output pins waveform formatters each shaping from the pin data distributed thereto by the pin data selector a test pattern signal having a waveform that meets standard requirements of a semiconductor device under test; timing calibrators calibrating signal propagation delay time values through respective rest pattern signal transmission paths connected to the respective waveform formatters; drivers transmitting the test pattern signals outputted from the respective timing calibrators to the output pins to which a semiconductor device under test is coupled; a computer system controlling operations of the testing apparatus; a timing measurement device measuring applied timings of the test pattern signals applied to the respective output pins; and a pin selection device connected to the output pins in a timing calibration mode and forming pin selection paths which selectively connect the respective output pins one by one to the timing measurement device; wherein said computer system comprises: memory means for storing therein signal propagation delay time values through the respective pin selection paths; subtraction means for subtracting the stored delay time values through the respective pin selection paths from corresponding total delay time values measured by means of the timing measurement device through respective series connections of the test pattern signal transmission paths and the pin selection paths corresponding to the respective output pins; and timing control means for controlling the signal propagation delay time values of the respective timing calibrators such that difference delay time values obtained as results of the subtraction means are converged to a predetermined constant value.
In the fourth aspect of the present invention, there is provided a semiconductor device testing apparatus having a timing calibration mode comprising: a pattern generator; a pin data selector distributing pin data including test pattern data, address signals and control signals, and outputted from the pattern generator to respective pin channels corresponding to output pins; waveform formatters each shaping from the pin data distributed thereto by the pin data selector a test pattern signal having a waveform that meets standard requirements of a semiconductor device under test; timing calibrators calibrating signal propagation delay time values through respective rest pattern signal transmission paths connected to the respective waveform formatters; drivers transmitting the test pattern signals outputted from the respective timing calibrators to the output pins to which a semiconductor device under test is coupled; a computer system controlling operations of the testing apparatus; a timing measurement device measuring applied timings of the test pattern signals applied to the respective output pins; and a pin selection device connected to the output pins in a timing calibration mode and forming pin selection paths which selectively connect the respective output pins one by one to the timing measurement device; wherein said computer system comprises: memory means for storing therein signal propagation delay time values through the respective pin selection paths; calculation means for calculating deviation values between the stored delay time value of the pin selection path stored in the memory means for one of the output pins which is determined as a reference output pin and the respective delay time values of the pin selection paths stored in the memory means for remaining output pins other than the reference output pin; and timing control means for controlling the delay time values of the respective timing calibrator such that deviation values between the total signal propagation delay time value for the reference output pin and the respective total signal propagation delay time values for the remaining output pins accord with the corresponding deviation values, respectively, whereby calibrating difference in signal propagation delay time values of the respective test pattern signal transmission paths.